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嵌入式OS--4G手机操作系统
嵌入式硬件设计
Altium Designer Layout高速硬件设计
开发语言/数据库/软硬件测试
芯片设计/大规模集成电路VLSI
其他类
 
  Synopsys DC-T培训
   入学要求

        学员学习本课程应具备下列基础知识:
        ◆ 电路系统的基本概念。

   班级规模及环境--热线:4008699035 手机:15921673576/13918613812( 微信同号)
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
近开课时间(周末班/连续班/晚班)
Synopsys DC-T培训:2024年11月18日......(欢迎您垂询,视教育质量为生命!)
   实验设备
     ☆资深工程师授课

         ☆注重质量 ☆边讲边练

        ☆合格学员免费推荐工作
        ★实验设备请点击这儿查看★
   新优惠
       ◆在读学生凭学生证,可优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
        3、培训合格学员可享受免费推荐就业机会。

  Synopsys DC-T培训
培训方式以讲课和实验穿插进行

课程描述:

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Overview

This workshop familiarizes you with the physical constraints that enable the strong DC-T correlation with physical tools. Through a combination of class lecture and hands-on labs, you will learn what the physical constraints are, how to load them into DC-T, how to view them, and how to verify they are complete and correct.

As part of the set up and run methodology, you will generate scripts using the Reference Methodology Script Generator (RMgen), and will adapt them to your design.

This workshop covers typical flows (flat, both with and without a floorplan, and hierarchical). It describes how the power and test flows fit into the DC-T flows. It covers methodologies that are common across all flows.

This workshop shows you how to setup for, analyze, and handle congestion, using text reports to quantify the congestion, and using the GUI to qualify it.

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Objectives

At the end of this workshop the student should be able to:

  • Load the physical input files to DC-T and list the actions to be taken on them
  • Configure and generate RMgen “seed scripts” ,??and adapt those scripts to your design
  • Understand three frequently-used DC-T flows:

·???Classic flat with Power and Test with a floorplan

·???Classic flat with Power and Test without a floorplan

·??Hierarchical

  • Use methodologies common to all flows
  • Navigate the GUI to explore a floorplan
  • Set up for the most accurate congestion analysis
  • Analyze congestion using both text and GUI
  • Recommend congestion fixes

Audience Profile

Engineers familiar with Design Compiler using wire load models.

Prerequisites

To benefit the most from the material presented in this workshop, students should:

●?Have taken the Design Compiler 1 Workshop

Course Outline

Unit 1

·??Physical Elements

·??Set up and Run

·??Common Flows

·??Congestion

Unit 2

???DC Synthesis and optimization techniques, questions and answers